Field of the Disclosure
The teachings in accordance with the exemplary embodiments of this present disclosure generally relate to an apparatus for controlling paralleled inverter.
Description of Related Art
In general, methods of using an inverter by expanding capacity of the inverter include a method in which a new product is designed by expanding voltage and current capacity of power elements, and a method of design in which already developed products are configured in parallel. There is a limit in developing a large capacity of inverter due to limited voltage and current capacity in power elements for industrial inverters, and paralleled inverters have been recently designed to overcome the disadvantage of prior art.
An accurate adjustment of synchronization at the output voltage is the key factor for paralleled inverters, and to this end, various technologies have been developed. In general, operation of a paralleled inverter is performed by one master controller and a plurality of slave controllers.
FIG. 1 is a block diagram illustrating a system of a paralleled inverter according to prior art, where a controller (100) in a conventional paralleled inverter system includes a master controller (110) and a slave controller (120). The slave controller (120) operates as a slave in a parallel operation, but operates as a master controller when an inverter B (320) is independently operated.
It is most important in the paralleled inverter to control a voltage at an output terminal on a same size and phase, and a paralleled reactor is used at an output terminal to prevent a circulating current from being generated by errors in size and phase. A coupled reactor (410) is used for a medium voltage inverter to avoid a problem of output voltage drop caused by installation of reactor.
In the inverter system of FIG. 1, each controller (110, 120) controls corresponding inverter A (200) and inverter B (300) for operation of unit inverter, but the master controller (110) in a paralleled operation controls an entire system and communicates with the slave controller (120) at all times. The master controller (110) transmits a synchronization signal to the slave controller (120) for output voltage synchronization.
FIG. 2 is an exemplary view illustrating a synchronization signal transmitted to the slave controller (120) by the master controller (110) of FIG. 1 and pulse width modulation (PWM) carriers of an inverter A and an inverter B thereof.
The synchronization signal transmitted by the master controller (110) is received by the slave controller (120), where the slave controller (120) resets a PWM carrier counter for adjustment of synchronization.
A 6600V multilevel medium voltage inverter includes power cells (200, 300) which are 18 single phase inverters in one inverter. Each power cell is operated through receipt of various pieces of information (size and phase of command, operation command, etc) by cell controllers (210, 310) from the controller (100).
However, the system of FIG. 1 requires hardware interface for transmission and receipt of synchronization signals between the master controller (110) and the slave controllers (120) for output voltage synchronization. This method of hardware interface is almost similar to the PWM synchronization, but there is a disadvantage of generating a signal delay on a circuit and of being influenced by noise generated from surrounding circuits.
Meanwhile, although synchronization may be performed by software synchronous algorithm, there is another disadvantage of generating a synchronization error as much as control period of CPU.